1. Field of the Invention
The present invention relates generally to output circuits for semiconductor integrated circuits, and more particularly, to output circuits having controllable load drive capability.
2. Description of the Background Art
Generally, various circuitry utilizing semiconductor devices comprises multiple semiconductor devices connected through interconnections. In other words, to implement a circuit function, multiple semiconductor devices are generally required. Accordingly, a number of semiconductor devices or elements are connected in parallel to an output terminal of a semiconductor device. The semiconductor device has an output buffer connected to its output terminal for driving these loads. The output buffer drives the load connected through the output terminal and an interconnection in response to the data signal to be output, generated within the semiconductor device. When the semiconductor device has a plurality of output terminals, each terminal is provided with an output buffer.
FIG. 11 shows a block diagram of conventional output buffer circuits 81 through 83 provided within the semiconductor device 8. Referring to FIG. 11, this semiconductor device 8 comprises a processing circuit 80 generating a data signal to be output in response to the input signal supplied through the input terminal, and output buffers 81 through 83 connected to receive the output data signal generated from the processing circuit 80. Each output buffer 81 through 83 drives the load connected to output terminals 101 through 103 respectively.
As previously described, the load is connected to each output terminal 101 through 103 of the semiconductor device 8 through an interconnecting line. An interconnection generally has a distributed parasitic capacitance with respect to ground. In addition to this, as a semiconductor device connected to an output terminal generally has an input capacitance, it is possible to equivalently express the load by way of capacitance including interconnection capacitance. Accordingly, as shown in FIG. 11, an equivalent lumped capacitance Cl through C3 is connected to each output terminal 101 through 103 through interconnections.
The conventional output buffers 81 through 83 have the same load drive capability. A load drive capability is defined as a current supply capability to a load. The values of each equivalent capacitance Cl through C3 connected to output terminals 101 through 103 are not necessarily the same because each output terminal 101 through 103 is connected to the different number of semiconductor devices through interconnections each having a different length. In the description below, it is assumed that the equivalent capacitances C1 through C3 satisfy the following relationship. EQU C1&lt;C2&lt;C3 . . . (1)
FIG. 12 shows a waveform diagram illustrating the change of the output signals respectively output from each output buffers 81 through 83 shown in FIG. 11. As described above, as the loads connected to each output terminal 101 through 103, (i.e., the values of equivalent capacitance Cl through C3) are different from each other, the waveforms of the output signals S1 through S3 output through the corresponding terminal are different. That is, a time required for a rise (a rise time) and a time required for a fall (a fall time) of each output signal Sl through S3 differs respectively.
Since the equivalent capacitance Cl having the smallest value is connected to the output terminal 101, the output signal Sl rises and falls quickly. Conversely, as the equivalent capacitance C3 having the largest value is connected to output terminal 103, the output signal C3 rises and falls slowly. As the equivalent capacitance C2 having an intermediate value is connected to the output terminal 102, the output signal S2 rises and falls at a speed intermediate the rise and fall time of signals Sl and S3.
It is pointed out that while each output buffer 81 through 83 thus has the same load drive capability, the times required for the output signals Sl through S3 to change differ responsive to the values of loads connected to output terminals 101 through 103. That is, since the loads, i.e., the equivalent capacitances Cl through C3 of different value are connected to corresponding output terminal 101 through 103 respectively, the time required to charge and discharge these equivalent capacitances Cl through C3 differs. Thus, as shown in FIG. 12, the waveforms of the output signals Sl through S3 are different.
As a result, for example, the timing at which the level of signal S3 reaches a logical "H" level is delayed with respect to the timing at which the signal Sl represents a logical "H" (assuming that processing circuit 80 shown in FIG. 11 requires a logical "H" at the same timing). Namely, as shown in FIG. 12, the times t.sub.H1, t.sub.H2 and t.sub.H3 at which respective output signals S1 through S3 represent a logical "H" are all different. Consequently, in the logic circuit connected to the output terminals 101 through 103, there is a possibility that an erroneous logical processing might be conducted over a period of time from time t.sub.H1 to time t.sub.H2 or to time t.sub.H3. That is, a timing error is brought about.
In addition, it is also pointed out that it is necessary for the load drive capability of the output buffer to be set to an optimum value. That is, in the case in which too large a load drive capability is set so as to minimize the rise time and the fall time, output signal overshoot, undershoot and ringing are likely to occur. This means it is necessary to set a load drive capability to an optimum value, i.e., to control the load drive capability . Moreover, setting too large a load drive capability in the output buffer results in increasing electric power consumption. Accordingly, controlling the load drive capability also makes it possible to control power consumption, i.e., to decrease power consumption.
There is a gate array as one example of the semiconductor device shown in FIG. 11. In the gate array, the capacitance of an aluminum interconnection connected to the output circuit is modified in order to change the load drive capability of the output circuit. That is, the interconnection pattern for the aluminum interconnection of the gate array is modified. For this purpose, two, i.e., large and small interconnection patterns for controlling the load drive capability of the output circuit are prepared in advance and one of them is selected as needed. In the conventional gate array, however, it is noted that the problems above can occur since the load drive capability of the output circuit cannot be controlled in a flexible manner.
As another example, there is a semiconductor device connected to a bus line in a computer system. It is noted that there is a possibility that the above-described problems may occur because the semiconductor device provided in the computer system has a fixed load drive capability as shown in FIG. 11.